1. Field of the Invention
The present invention relates to a signal level conversion circuit and, more specifically, to a signal level conversion circuit for performing a differential operation and a semiconductor device provided with the same as an input buffer.
2. Description of the Background Art
Generally, a semiconductor device such as a memory device is provided with an input buffer generating an internal signal in accordance with an externally applied input signal. The input buffer converts the potential level of the external signal in a specific range to fall within a range suitable for the internal operation of the semiconductor device.
In this case, the level of the internal signal is set based on a correlationship between the potential of the external signal and a reference potential. If, for example, L and H level potentials of the internal signal are respectively Vss and Vdd, the reference potential is determined as (Vdd+Vss)/2, and the potential of the external signal is compared with the reference potential for setting the level of the internal signal.
In a semiconductor device such as a DDR (Double Data Rate)-SDRAM (Synchronous Dynamic Random Access Memory), which operates in response to both activation and inactivation edges of an external clock EXT.CLK used as a reference, external clock EXT.CLK and its inverted clock /EXT.CLK are input and an internal clock signal is generated based on a correlationship between the potential levels of external clock signal EXT.CLK and inverted clock /EXT.CLK using inversion clock /EXT.CLK as a reference.
The generation of the internal signal at the input buffer is accompanied by a delay required for converting a correlationship between the potentials of the external and reference signals (potential difference) to the level of the internal signal. Thus, at the input buffer, as the potential levels of the input external signal and reference signal vary, the delay caused by the generation of the internal signal also varies. In a high speed device such as the above mentioned DDR-SDRAM, the timing of an output signal must be strictly adjusted with respect to the timing of an input signal, and therefore variation in delay of the internal signal at the input buffer cannot be ignored. In view of the above, an input buffer which is less affected by variation in the potential level of an input external signal is required.
FIG. 9 is a circuit diagram showing a structure of a general differential input buffer 300 used for a semiconductor device.
Referring to FIG. 9, input buffer 300 receives an external signal such as an external clock EXT.CLK and a reference signal Vr, and differentially amplifies the potential difference thereof for generating an internal clock INT.CLK of an internal signal. H and L level potentials of the internal signal are respectively a power supply potential Vdd and a ground potential Vss. Reference signal Vr is for example an inverted clock /EXT.CLK of external clock EXT.CLK or a constant direct current potential VREF at a level intermediate between power supply potential Vdd and ground potential Vss.
Input buffer 300 includes P type MOS transistors QP1 and QP2 respectively arranged between power supply potential Vdd and nodes Na, Nb; and N type MOS transistors QN1 and QN2 respectively arranged between a common node Nc and nodes Na, Nb. Transistors QP1 and QP2 have their gates connected to node Na. Transistors QN1 and QN2 have their gates respectively receiving a reference signal Vr and an external signal.
Input buffer 300 further includes an N type MOS transistor QNc electrically connected between common node Nc and ground potential Vss and having its gate receiving a constant direct current potential Vmn. Direct current potential Vmn is set at an intermediate potential level higher than a threshold value of transistor QNc. Thus, transistor QNc serves as a constant current source and supplies an operation current for differential amplification.
Transistors QN1, QN2, QP1, QP2, and QNc form a so-called current mirror amplifier.
If the gate potentials of transistors QN1 and QN2 are the same, currents i1 and i2 flowing through these transistors remain unchanged, having a value half a current i0 flowing through transistor QNc. Then, the potential level at node Nb generating the internal signal converges to a level where currents flowing through transistors QP1 and QP2 serving as a load equal to currents flowing through transistors QN1 and QN2.
Even if the gate potentials of transistors QN1 and QN2 vary, as long as the potentials thereof are the same, i.e., there is no potential difference, currents i1 and i2 have the same value, i.e., half current i0. Thus, the potential level at node Nb remains constant. Accordingly, when the external signal and reference signal change in the same manner, the internal operation of the input buffer would not be affected by variation in external potential level. In other words, a delay caused by the generation of the internal signal remains constant.
If the gate potential of transistor QN2, i.e., the potential of the external signal, increases to a level slightly above the gate potential of transistor QN1, i.e., the potential of the reference signal, current i2 flowing through transistor QN2 increases and current i1 flowing through transistor QN1 correspondingly decreases. On the other hand, since current i0 flowing through the circuit as a whole remains unchanged, the potential level at node Nb decreases in accordance with magnitudes of increase in current i2 of transistor QN2 and a load.
Conversely, if the gate potential of transistor QN2 decreases to a level slightly below the gate potential of transistor QN1, current i2 flowing through transistor QN2 decreases but current i1 flowing through transistor QN1 increases. Since current i0 flowing through the circuit as a whole remains unchanged, in this case, the potential level of internal node Nb increases in accordance with magnitudes of decrease in current i2 of transistor QN2 and a load. Thus, the internal signal generated at node Nb amplifies the gate potential difference between transistors QN1 and QN2, but does not affect in-phase component or direct current component.
However, to achieve stable operation of differential input buffer 300 with a high voltage gain, transistors QN1, QN2, QP1, QP2, and QNc, forming a current mirror amplifier, must operate in a saturation region.
Particularly, current supply transistor QNc serves as a constant current source through operation in the saturation region. To allow operation of current supply transistor QNc in the saturation region, the drain potential thereof, i.e., the potential level at common node Nc must equal Vmnxe2x88x92Vth (Vth: threshold voltage of transistor QNc). Generally, the potential level at common node Nc must be about several hundreds of mili-volts to assure operation current for a differential operation.
Further, the operation of transistor QN2 in the saturation region requires that the gate potential of transistor QN2, i.e., the potential of the external signal, must be at least a level higher by Vthxe2x80x2 (Vthxe2x80x2: a threshold voltage of transistor QN2) than the potential level at common node Nc. Assume that Vth is about 0.7V, as in a usual case. To ensure that transistor QN2 always operates in the saturation region, the gate potential must be at least about 1.0V regardless of the level of the external signal.
Recently, driving potentials and signal amplitude levels of interface systems have been on the decrease along with power supply potentials for the purpose of reducing power consumption. Thus, at a lower limit of a specified range of potential level, the gate potential of transistor QN2 cannot attain a sufficient level. As a result, a stable differential amplification operation cannot be achieved by input buffer 300.
In an SSTL2 (Stub Series Terminated Logic for 2.5V) as one of typical interface standards applied to a DDR-SDRAM device, for example, a power supply potential is set at 2.3V to 2.7V, so that a reference potential is set at 1.15V to 1.35V, which is half the power supply potential. The minimum amplitude of an AC (Alternating Current) signal is set at xc2x10.35V in the SSTL2. In other words, to comply with the SSTL2 standard, the AC signal of 1.15Vxc2x10.35V must also be input while appropriately identifying the H or L level thereof.
Thus, in inputting an L level corresponding to the minimum amplitude at the lower limit 1.15V, the gate potential of transistor QN2 would be 0.8V, which is lower than the gate potential required for the operation in the saturation region as previously mentioned. In this situation, input buffer 300 cannot perform a desired differential operation.
FIG. 10 shows another exemplary structure of a conventional differential input buffer.
Referring to FIG. 10, an input buffer 310 differs from input buffer 300 shown in FIG. 9 in that it has a current supply transistor QPc formed of a P type MOS transistor and arranged on the side of power supply potential Vdd. P type MOS transistors QP1 and QP2 as well as N type MOS transistors QN1 and QN2 are arranged between a common node Nd and ground potential Vss. An external signal and a reference signal Vr are respectively applied to the gates of transistors QP2 and QP1. Transistors QN1 and QN2 have their gates connected to a node Na. Thus, the N type MOS transistor serves as a load at input buffer 310. For differential input buffer 310, similarly, transistors QN1, QN2, QP1, QP2, and QPc that form a current mirror amplifier must be operated in the saturation region to ensure a stable operation with a high voltage gain.
In the previous discussion of FIG. 9, it has been described that a sufficient differential operation of input buffer 300 may not be achieved even in the range specified by interface standard SSTL2. A similar problem may arise in the case of input buffer 310. More specifically, if the potential level of an input signal reaches an upper limit when the power supply potential is at a lower limit, similarly, a sufficient gate potential of transistor QP2 cannot be ensured. As a result, the transistors forming the current mirror amplifier cannot operate in the saturation region, whereby input buffer 310 cannot perform a desired differential operation.
Thus, a potential difference between the reference signal used for identifying the level of the external signal and one of power supply potential Vdd and ground potential Vss respectively corresponding to the H and L levels of the internal signal becomes small, the differential input buffer cannot generate the internal signal by a perfect differential operation. As a result, the operation speed of the input buffer, i.e., a delay caused by the generation of the internal signal, disadvantageously varies. Consequently, the general operation becomes unstable if a timing accuracy is strictly required for a semiconductor device provided with such an input buffer.
An object of the present invention is to provide a signal level conversion circuit suitable for an input buffer of a semiconductor device which stably generates an internal signal at high speed by a differential operation independent of a range of potential level of an input external signal.
In short, the present invention is a signal level conversion circuit generating an output signal based on a correlationship between the potentials of an input signal and a reference signal. The signal level conversion circuit includes a differential amplification circuit and a bias circuit. The differential amplification circuit amplifies a potential difference between a first node receiving the input signal and a second node receiving a reference signal for generating an output signal. The bias circuit applies bias potential to each of the first and second nodes.
According to another aspect, the present invention is a semiconductor device for operation which is provided with an input buffer generating an internal signal based on a correlationship between the potentials of an external signal and a reference signal. The input buffer includes: a differential amplification circuit amplifying the potential difference between a first node receiving the external signal and a second node receiving the reference signal for generating an internal signal; and a bias circuit applying bias potential to each of the first and second nodes.
According to still another aspect, the present invention is a signal level conversion circuit generating an output signal based on a correlationship between the potentials of an input signal and a reference signal. The signal level conversion circuit includes a differential amplification circuit, a first low pass filter, a first bias circuit, a first high pass filter, and a second bias circuit.
The differential amplification circuit amplifies a potential difference between first and second nodes for generating an output signal. The first low pass filter transmits a frequency component of the input signal that is at most a prescribed frequency. The first bias circuit applies a first bias potential to the first node in accordance with an output potential of the first low pass filter. The first high pass filter transmits to the first node a frequency component of the input signal that is at least a prescribed frequency. The second bias circuit applies a second bias potential to the second node in accordance with the potential level of the reference signal. A relationship between the first bias potential and the output potential of the first low pass filter is similar to that between the second bias potential and the potential level of the reference signal.
Therefore, a main advantage of the present invention is that an output signal can be generated by a desired differential amplification operation even if the amplitude of an input signal is low because a potential at the input node of a differential amplification circuit is set at least to a prescribed potential and variations in potential levels of a reference signal and the input signal can be reflected in the input node of the differential amplification circuit.
Further, in the input buffer generating an internal signal of the semiconductor device in accordance with an external signal, the potential at the input node of the differential amplification circuit is set at least to a prescribed potential, so that variations in signal levels of the reference signal and external signal can be reflected in the input node of the differential amplification circuit. Thus, even if the amplitude of the external signal is low, the internal signal can be generated by the desired differential amplification operation.
Moreover, the potential at the input node of the differential amplification circuit is set at least to a prescribed potential, so that both low and high frequency components of the input signal can be superimposed for transmission to the input node of the differential amplification circuit. As a result, even if the potential level of the input signal irregularly varies independently of a given frequency, an output signal can be generated in accordance with the variation in potential level of the input signal by a desired differential amplification operation.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.